From nanometers to Angstroms: why Intel wants to change the term by which semiconductor breakthroughs are measured

Amelie Looker
4 Min To Read
Wednesday, Apr 27, 2022

There was a time when you could tell if your processor was more powerful than the previous one by the megahertz or gigahertz of speed it had. Gradually, that scale changed and we started talking about nanometers: the lower the number, the more advanced the chip.

Pat Gelsinger, CEO of Intel, wants us to stop talking about nanometers and start talking about Angstroms and has unveiled a timetable to get us used to this new designation.

Five next generations

Earlier this year, CEO Pat Gelsinger announced Intel’s new IDM 2.0 strategy.

The goal was to continue working on the development of Intel’s process node technology, going beyond the current 10 nm designs in production today. In addition, the company was open to manufacturing for third parties and licensing its products to regain its position in the market.

Although Intel claims it is already producing more 10nm wafers in a day than 14nm, the company has struggled to make the transition to 10nm, while other competitors, such as TSMC, seem to have these farbrication models settled.

Intel changes the name of the nodes

In publishing its schedule for the next few years, Intel is also changing some names.

The company claims that there is some confusion and that its “Intel 10nm” is equivalent to “TSMC 7nm”. So Intel is changing the name of its future process nodes.

The new naming scheme means that what would have been Intel’s third-generation 10nm chips will now be called “Intel 7”. While at first glance it might seem like a way for Intel to position its upcoming 10-nanometer chips as more competitive next to its rivals’ 7-nm products, some analysts claim that this naming is more realistic compared to its competitors.

Upcoming releases

The current generation technology in use is Tiger Lake, known as Intel 10nm SuperFin (10SF). According to the schedule released by Intel, these will be the next product launches and the expected dates:

Intel 7, second half of 2021: formerly known as 10nm Enhanced Super Fin or 10ESF. Alder Lake and Sapphire Rapids will now be known as Intel 7nm products, showing 10-15% higher performance per watt over 10SF due to transistor optimizations. Alder Lake is currently in volume production. Intel’s Xe-HP will now be known as an Intel 7 product.
Intel 4, second half of 2022: formerly known as Intel 7nm. Intel stated earlier this year that its Meteor Lake processor will use this process node technology. Intel expects 20% higher performance per watt over the previous generation. Intel’s upcoming scalable Xeon product, Granite Rapids, will also use an Intel 4-based compute tile.
Intel 3, second half of 2023 H2: formerly known as Intel 7+. This is where Intel’s strategy becomes more modular: Intel 3 will share some Intel 4 features, but will be new enough to describe this entire new node, in particular new high-performance libraries. Intel expects 18% higher performance per watt over Intel 4.
Intel 20th, 2024: formerly known as Intel 5nm. Moving to two-digit designation, with the A for Ångström. Few details have been released, but this is where Intel will be moving from FinFETs to its version of Gate-All-Around-All-Around (GAA) transistors called RibbonFETs. Also Intel will introduce a new PowerVia technology.
Intel 18th, 2025: Intel expects to have an 18A process in 2025. 18A will use machines that are capable of more accurate photolithography. This is where Intel expects to have an unquestioned leadership.

Intel has confirmed that Intel 3 and Intel 20A will be offered to foundry customers (but has not indicated whether Intel 4 or Intel 7 will be offered).

What are Ångström’s

Ångstroms are units of measurement smaller than nanometers. It is said that 20Å equals 2 nm or 10A equals 1 nm. The first chip to be measured in Ångstroms will be the Intel 20A, with a completely new architecture called RibbonFET.

It is a fundamentally new transistor technology that will enable higher density and smaller sizes, according to Gelsinger. It will also incorporate a new “PowerVia” technology that makes it possible for silicon wafers to be powered from the back of the chip, rather than routed to the front.